Method of programming in a flash memory device

ABSTRACT

A method of programming a flash memory device includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, and verifying whether the first memory cell is programmed through a first verifying voltage. The first program voltage that is repeatedly increased by a step voltage when the first memory cell is not programmed. A second memory cell coupled to an odd bit line is programmed by applying the first program voltage to the word line. Whether the second memory cell is programmed is verified using a second verifying voltage that is higher than the first verifying voltage. The second memory cell is programmed using a program voltage that is repeatedly increased by the step voltage when the second memory cell is not programmed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/962,049, filed Dec. 20, 2007, which claims priority from KoreanPatent Application No. 2007-78556, filed on Aug. 06, 2007, the contentsof which are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a method of programming a flash memorydevice. More particularly, the present invention relates to a method ofprogramming which reduces a threshold voltage imbalance due tointerference effects in the flash memory device.

Recently, the demand has increased for a non-volatile memory devicewhich electrically programs and erases data, and does not require arefresh function for periodically rewriting data.

In addition, high integration techniques for a memory device have beenstudied so as to develop a high capacity memory device (e.g., flashmemory device).

Generally, a flash memory device is divided into a NAND flash memory anda NOR flash memory. In the NOR flash memory, each of the memory cells isconnected independently to a bit line and a word line, and so the NORflash memory has excellent random access time. Whereas, in the NANDflash memory, only one contact is required for one cell string becausememory cells are connected in series, and so the NAND flash memory hasexcellent characteristics for integration. Accordingly, the NAND flashmemory has been generally employed in high density flash memory.

Recently, multi-bit cells for storing a plurality of data bits in onememory cell have been actively studied so as to enhance the degree ofintegration of the above flash memory. This memory cell is referred toas a multi-level cell (hereinafter, referred to as “MLC”). A memory cellfor storing one data bit is referred to as a single level cell (SLC).

Since the MLC has at least four threshold voltage levels compared to anSLC which has two threshold voltage levels, the MLC can increase thenumber of bits by two or more times over the SLC.

On the other hand, it is important to reduce a change in the thresholdvoltage of a cell so as to embody the MLC. Here, one of the causes forthe change is an interference effect due to capacitance between cells.

FIG. 1 is a view illustrating a threshold voltage distribution relatedto a conventional method of programming in a flash memory device.

Generally, a memory cell array included in the flash memory device has acell string structure in which memory cells are connected in series,wherein the memory cells are connected to an even bit line or an odd bitline. Here, the odd bit line is adjacent to the even bit line.

In a program operation of the flash memory device, a first memory cellis programmed by applying a program voltage (e.g., 15V) to a word lineof the first memory cell connected to the even bit line, and so thefirst memory cell has a threshold voltage distribution as shown in A ofFIG. 1.

Subsequently, a second memory cell connected to the odd bit lineadjacent to the first memory cell is programmed by applying the programvoltage (e.g., 15V) to a word line of the second memory cell, and so thesecond memory cell has a threshold voltage distribution as shown in A′of FIG. 1. In this case, the threshold voltage distribution of the firstmemory cell is shifted from A into B due to the interference effect whenthe second memory cell is programmed.

This change of the threshold voltage distribution deteriorates programcharacteristics of the flash memory device. Specially, sensing margin isreduced due to the change of the threshold voltage distribution in theMLC flash memory device.

SUMMARY OF THE INVENTION

It is a feature of the present invention to provide a method ofprogramming in a flash memory device for performing a program operationrelated to an even bit line using a second verifying voltage smallerthan a first verifying voltage so that threshold voltage distribution issmaller than usual threshold voltage distribution, wherein the firstverifying voltage relates to a program operation of an odd bit line, andthe second verifying voltage relates to the program operation of theeven bit line. Then, threshold voltage distribution of a memory cellcoupled to the even bit line is shifted into normal threshold voltagedistribution due to an interference effect in accordance with a programvoltage used when the program operation related to the odd bit line isperformed. As a result, the memory cell coupled to the even bit line hasthe same threshold voltage distribution as a memory cell coupled to theodd bit line.

A method of programming in a flash memory device using ISPP programmethod according to on an embodiment of the present invention includesprogramming a first memory cell coupled to an even bit line using afirst program voltage increased in sequence by a first step voltage; andprogramming a second memory cell coupled to an odd bit line using asecond program voltage increased in sequence by a second step voltage,wherein the second step voltage is higher than the first step voltage.

A method of programming in a flash memory device according to anotherembodiment of the present invention includes programming a first memorycell by applying a first program voltage to a word line related to thefirst memory cell coupled to a first bit line; applying a second programvoltage higher by a first step voltage than the first program voltage tothe word line in case that the first memory cell is not programmed, andprogramming the first memory cell by applying new program voltageincreased by the first step voltage until the first memory cell isprogrammed; programming a second memory cell by applying the firstprogram voltage to a word line related to the second memory cell coupledto a second bit line, wherein the second bit line is adjacent to thefirst bit line; and applying a program voltage higher by a second stepvoltage than the first program voltage to the word line in case that thesecond memory cell is not programmed, and programming the second memorycell by applying new program voltage increased by the second stepvoltage until the second memory cell is programmed, wherein the secondstep voltage is higher than the first step voltage.

A method of programming in a flash memory device according to stillanother embodiment of the present invention includes performing a firstprogram operation so that threshold voltage of a first memory cellcoupled to a first bit line is increased to a first voltage smaller thanan objection voltage; and performing a second program operation so thatthreshold voltage of a second memory cell coupled to a second bit lineis increased to a second level identical to or higher than the objectionvoltage and the threshold voltage of the first memory cell is increasedto a third level identical to or higher than the objection voltage.

A method of programming in a flash memory device according to stillanother embodiment of the present invention includes programming a firstmemory cell by applying a first program voltage to a word line relatedto the first memory cell coupled to a first bit line; verifying whetheror not the first memory cell is programmed by applying a first verifyingvoltage smaller than an objection voltage to the word line; programminga second memory cell by applying a second program voltage to a word linerelated to the second memory cell coupled to a second bit line adjacentto the first bit line; and verifying whether or not the second memorycell is programmed by applying a second verifying voltage identical tothe objection voltage to the word line.

A method of programming in a flash memory device according to stillanother embodiment of the present invention includes programming a firstmemory cell coupled to an even bit line by applying a first programvoltage to a word line; verifying whether or not the first memory cellis programmed through a first verifying voltage, and programming thefirst memory cell using a program voltage increased in sequence by astep voltage than the first program voltage in case that the firstmemory cell is not programmed; programming a second memory cell coupledto an odd bit line by applying the first program voltage to the wordline; and verifying whether or not the second memory cell is programmedthrough a second verifying voltage higher than the first verifyingvoltage, and programming the second memory cell using a program voltageincreased in sequence by the step voltage than the first program voltagein case that the second memory cell is not programmed.

As described above, a method of programming in a flash memory deviceperforms a program operation related to an even bit line using a secondverifying voltage smaller than a first verifying voltage so thatthreshold voltage distribution is smaller than usual threshold voltagedistribution, wherein the first verifying voltage relates to a programoperation of an odd bit line, and the second verifying voltage relatesto the program operation of the even bit line. Then, threshold voltagedistribution of a memory cell coupled to the even bit line is shiftedinto normal threshold voltage distribution due to an interference effectin accordance with a program voltage used when the program operationrelated to the odd bit line is performed. As a result, the memory cellcoupled to the even bit line may have the same threshold voltagedistribution as a memory cell coupled to the odd bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating a threshold voltage distribution relatedto a conventional method of programming in a flash memory device;

FIG. 2 is a view illustrating a memory cell array in a flash memorydevice according to a first embodiment and a second embodiment of thepresent invention;

FIG. 3 is a view illustrating threshold voltage distribution in a methodof programming a flash memory device according to a first embodiment ofthe present invention; and

FIG. 4 is a view illustrating threshold voltage distribution in a methodof programming a flash memory device according to a second embodiment ofthe present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, the embodiments of the present invention will be explainedin more detail with reference to the accompanying drawings.

FIG. 2 is a view illustrating a memory cell array in a flash memorydevice according to a first embodiment and a second embodiment of thepresent invention. FIG. 3 is a view illustrating threshold voltagedistribution in a method of programming a flash memory device accordingto a first embodiment of the present invention.

Hereinafter, a method of programming in the flash memory deviceaccording to the first embodiment of the present invention will bedescribed in detail with reference to drawings FIG. 2 and FIG. 3. It isdesirable that the method uses an incremental step pulse programming(ISPP) method.

Firstly, a first memory cell MC1 coupled to an even bit line isprogrammed. Particularly, a first program voltage is applied to a wordline coupled to the first memory cell MC1. A pass voltage is applied toword lines not connected to the first memory cell MC1 so as to preventprogram of those memory cells.

Subsequently, it is verified whether or not the first memory cell MC1 isprogrammed by applying a verifying voltage Vverify to a correspondingword line in a verifying operation.

If it is verified that the first memory cell MC1 is programmed, theprogram operation is ended. However, if it is verified that the firstmemory cell MC1 is not programmed, a second program voltage higher thanthe first program voltage is applied to the word line. In one embodimentof the present invention, a difference in the first program voltage andthe second program voltage (i.e., first step voltage) is 0.15V to 0.5V,preferably 0.3V.

Thereafter, if it is verified that the first memory cell MC1 isprogrammed by the verifying operation, the program operation is ended.However, if it is verified that the first memory cell MC1 is notprogrammed by the verifying operation, the program operation isperformed again by applying a third program voltage higher than thesecond program voltage by the first step voltage to the word line. Theprogram and the verifying operation are repeatedly performed until thefirst memory cell MC1 is programmed.

Once the first memory cell MC1 has been programmed, the first memorycell MC1 has threshold voltage distribution as shown in C of FIG. 3.Here, the threshold voltage distribution of the first memory cell MC1has a narrow width because the first step voltage smaller than aconventional step voltage is used. The conventional step voltage is 0.5V to 1.0 V.

Subsequently, a second memory cell MC2 coupled to the odd bit line BLois programmed. A pass voltage is applied to word lines not connected tothe second memory cell MC2 so as to prevent program of those memorycells.

Then, it is verified whether or not the second memory cell MC2 isprogrammed by performing a verifying operation.

If it is verified that the second memory cell MC2 is programmed, theprogram operation is ended. However, if it is verified that the secondmemory cell MC2 is not programmed, a second program voltage higher thanthe first program voltage is applied to the word line. Here, thedifference of the first program voltage and the second program voltage(i.e., second step voltage) is greater than the first step voltage usedin the process of programming the first memory cell MC1 coupled to theeven bit line BLe. For example, the second step voltage is 0.15V to0.5V, preferably 0.4V. The second step voltage is greater than the firststep voltage by about 0.1V in the present embodiment. In anotherembodiment, the difference is 0.07V. In yet another embodiment, thedifference is 0.13V, 0.15, or 0.18V. The program and the verifyingoperation are repeatedly performed until the second memory cell MC2 isprogrammed.

The threshold voltage distribution of the programmed first memory cellMC1 is shifted from C into D due to the interference effect (ordisturbance effect or program disturb) in accordance with the programvoltage used when the second memory cell MC2 is programmed. In otherwords, the threshold voltage distribution of the first memory cell MC1is shifted to have substantially the same threshold voltage distributionas the second memory cell MC2. As a result, threshold voltagedistributions of the memory cells MC1 and MC2 coupled to the bit linesBLe and BLo are improved.

FIG. 4 is a view illustrating threshold voltage distribution in a methodof programming a flash memory device according to a second embodiment ofthe present invention.

Hereinafter, the method of programming a flash memory device accordingto the second embodiment of the present invention will be described indetail with reference to FIG. 2 and FIG. 4. It is desirable that themethod uses the ISPP method.

Firstly, a first memory cell MC1 coupled to the even bit line BLe isprogrammed. Particularly, a first program voltage is applied to a wordline coupled to the first memory cell MC1. A pass voltage is applied toword lines not connected to the first memory cell MC1 so as to preventprogram of those memory cells.

Subsequently, it is verified whether or not the first memory cell MC1 isprogrammed through a verifying operation. Here, the verifying operationis performed by applying a first verifying voltage Vverify1 to the wordline connected to the first memory cell MC1 and detecting a voltage ofthe even bit line BLe.

That is, the program of the first memory cell MC1 is verified throughdetection as to whether a precharged even bit line BLe is discharged ormaintains its voltage level when the first verifying voltage Vverify1 isapplied. Here, it is desirable that the first verifying voltage Vverify1is smaller than a second verifying voltage Vverify2 used when a secondmemory cell MC2 coupled to the odd bit line BLo is verified. In thepresent embodiment, the second verifying voltage Vverify2 has the samevoltage as the conventional verifying voltage Vverify.

If it is verified that the first memory cell MC1 is programmed, theprogram operation is ended. However, if it is verified that the firstmemory cell MC1 is not programmed, a second program voltage higher thanthe first program voltage is applied to the word line of the firstmemory cell MC1. Here, the step voltage is 0.3V. The program operationand the verifying operation are repeatedly performed until the firstmemory cell MC1 is programmed. The first verify voltage Vverify1 is usedfor the verification step during this stage.

Once the first memory cell MC1 has been programmed, the first memorycell MC1 has a threshold voltage distribution as shown in E of FIG. 4.

Subsequently, the second memory cell MC2 coupled to the odd bit line BLois programmed. Here, a pass voltage is applied to word lines notconnected to the second memory cell MC2 so as to prevent program ofthose memory cells.

Then, it is verified whether or not the second memory cell MC2 isprogrammed. Here, it is desirable that the second verifying voltageVverify2 is higher than the first verifying voltage Vverify1. In thepresent embodiment, the second verifying voltage Vverify2 is higher thanthe first verifying voltage Vverify1.

If it is verified that the second memory cell MC2 is programmed, theprogram operation is ended. However, if it is verified that the secondmemory cell MC2 is not programmed, a second program voltage higher thanthe first program voltage is applied to the word line of the secondmemory cell MC2. The program and the verifying operation are repeatedlyperformed until the second memory cell MC2 is programmed.

The threshold voltage distribution of the programmed memory cell MC2 islocated in a more right direction compared to the threshold voltagedistribution of the programmed memory cell MC1 by performing the programoperation using the second verifying voltage Vverify2 higher than thefirst verifying voltage Vverify1 used when the first memory cell MC1 isprogrammed.

The threshold voltage distribution of the first memory cell MC1 isshifted from E into F due to the interference effect in accordance withthe program voltage used when the second memory cell MC2 is programmed.As a result, the first memory cell MC1 has substantially the samethreshold voltage distribution as the second memory cell MC2.Accordingly, the threshold voltage distributions of the memory cells MC1and MC2 coupled to the bit lines BLe and BLo are improved.

In the embodiments above, the memory cells are described as beinggrouped together in a unit of even and odd bit lines (or even and oddcell strings). As will be understood by those skilled in the art, thepresent invention is not limited to a memory cell array having such aconfiguration. As used herein, the even and odd bit lines (or cellstrings) refer to bit lines (or cell strings) that are adjacent to eachother. For example, the memory cells may be grouped together in a unitof three or more bit lines.

Any reference in this specification to “one embodiment,” “anembodiment,” “example embodiment,” etc., means that a particularfeature, structure, or characteristic described in connection with theembodiment is included in at least one embodiment of the invention. Theappearances of such phrases in various places in the specification arenot necessarily all referring to the same embodiment. Further, when aparticular feature, structure, or characteristic is described inconnection with any embodiment, it is submitted that it is within thepurview of one skilled in the art to affect such feature, structure, orcharacteristic in connection with other ones of the embodiments.

Although embodiments have been described with reference to a number ofillustrative embodiments thereof, it should be understood that numerousother modifications and embodiments can be devised by those skilled inthe art that will fall within the spirit and scope of the principles ofthis disclosure. More particularly, various variations and modificationsare possible in the component parts and/or arrangements of the subjectcombination arrangement within the scope of the disclosure, the drawingsand the appended claims. In addition to variations and modifications inthe component parts and/or arrangements, alternative uses will also beapparent to those skilled in the art.

1. A method of programming a flash memory device, the method comprising:programming a first memory cell by applying a program voltage; verifyingwhether the first memory cell is programmed by applying a firstverifying voltage; programming a second memory cell by applying theprogram voltage; and verifying whether the second memory cell isprogrammed by applying a second verifying voltage.
 2. The method ofclaim 1, wherein the second verifying voltage is greater than the firstverifying voltage.
 3. The method of claim 1, wherein the first memorycell and second memory cells are coupled to a word line.
 4. The methodof claim 1, wherein a bit line of the first memory cell is adjacent to abit line of the second memory cell.
 5. A method of programming a flashmemory device, the method comprising: programming a first memory cell byapplying a first program voltage; verifying whether the first memorycell is programmed by applying a first verifying voltage; programming asecond memory cell by applying a second program voltage; and verifyingwhether or not the second memory cell is programmed by applying a secondverifying voltage, wherein the second verifying voltage is greater thanthe first verifying voltage.
 6. The method of claim 5, wherein a levelof the first program voltage is the same as a level of the secondprogram voltage.
 7. The method of claim 5, wherein a level of the firstprogram voltage is different than a level of the second program voltage.8. The method of claim 5, wherein the first memory cell and secondmemory cells are coupled to a word line.
 9. The method of claim 5,wherein a bit line of the first memory cell is adjacent to a bit line ofthe second memory cell.
 10. A method of programming a flash memorydevice, the method comprising: programming a first memory cell byapplying a first program voltage; verifying whether the first memorycell is programmed by applying a first verifying voltage; programming asecond memory cell by applying a second program voltage; and verifyingwhether the first memory cell is programmed by applying a secondverifying voltage, wherein the first memory cell and second memory cellare coupled to a word line.
 11. The method of claim 10, wherein thesecond verifying voltage is greater than the first verifying voltage.12. The method of claim 10, wherein a level of the first program voltageis the same as a level of the second program voltage.
 13. The method ofclaim 10, wherein a level of the first program voltage is different thana level of the second program voltage.
 14. The method of claim 10,wherein a bit line of the first memory cell is adjacent to a bit line ofthe second memory cell.